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Senior FPGA Design Engineer

2 months ago

Abu Dhabi, Abu Dhabi, United Arab Emirates Edge Group Full time
About EDGE

EDGE is a pioneering technology group that specializes in developing innovative solutions for defense and beyond. Our mission is to push the boundaries of what is possible and create a secure future for all.

We are committed to fostering a collaborative environment where our people can thrive and make a real impact. Our team is dedicated to leveraging advanced technologies such as autonomous capabilities, cyber-physical systems, and directed energy to artificial intelligence.

Key Responsibilities
  • Design and implement layer 1/PHY radio front-end algorithms for FPGA
  • Develop and maintain HDL code to implement FPGA solutions
  • Implement layer 2 algorithms for running on Microcontroller
  • Design using combinational-logic-design and synchronous-circuits
  • Write test benches and use verification tools such as ModelSim
  • HDL design synthesis and implementation
  • Use vendor tools for timing closure, floor planning, and design constraints
  • Develop solutions for real-time embedded systems related to radar and communication links
  • Use vendor design tools such as Libero and/or Vivado
  • Integrate FPGA peripherals and modules such as timers, ADCs, DACs, communication transceivers, PWM controllers, DDR memories, and LVDS interface
  • Use programming languages for MCU, such as C/C++ and assembly languages
  • Build Linux images such as Yocto and FreeRTOS
  • Design and generate BSP for the SoC in use
  • Lead and mentor junior engineers, foster a collaborative environment, and share knowledge
  • Stay up-to-date with advancements in embedded technologies and best practices
  • Use version-controlled environment such as Git or SVN
  • Code writing discipline such as commenting and bug tracking
  • Conduct hardware testing and troubleshooting using oscilloscopes and logic analysers
Requirements
  • Bachelor's or master's degree in computer science, communication, electronic, or software engineering
  • Minimum 10 years of experience in VHDL code writing
  • Knowledge and understanding of layer 1/PHY and layer 2 radio front-end algorithm implementation
  • Knowledge and understanding of Verilog
  • Knowledge and understanding of Yocto
  • Exposure to DO-254 development methodology